1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to compound junctionless field effect transistors compatibly formed on a silicon substrate as compound semiconductor devices.
2. Description of the Related Art
A conventional field effect transistor, as shown in FIG. 1, is a MOSFET having a MOS structure as a Metal (gate electrode)-Oxide (gate dielectric layer)-Silicon (channel region) structure, consisting of source 210 and drain 220 regions formed by implanting with a dopant of a second conductive type (e.g., n-type) in a silicon substrate of a first conductive type (e.g., p-type) and a gate electrode 400 being separated by a gate dielectric layer 300 and located over a channel region between the source and drain regions.
In the conventional field effect transistor mentioned above, junctions 120 can be come into being due to the source 210 and drain 220 regions formed by a dopant implantation and the junctions form a depletion region (not shown) by pn junctions.
By the being of the depletion regions, a voltage applied to the source and drain electrodes 500 and 600 can generate a current only flowing through a channel formed below the gate electrode 400. Namely, there is an effect being insulated by the depletion regions between the source region 210 and the other part of the silicon substrate 100 as a body region and between the drain region 220 and the body region.
However, there are some problems by the being of the depletion regions. It is a problem that a leakage current is induced in the depletion region formed on the side of the drain region by an impact ionization due to the collision of hot carriers or by the generation of electron-hole pairs due to the tunneling occurred in the overlapping part of the gate electrode and the drain region by a voltage difference between the gate electrode and the drain electrode. Also, it is another problem that the operation of a high frequency such as a cut-off frequency or a power transmission maximum frequency and the like is restricted by the being of the depletion region.
To solve the problems of the conventional MOSFET structure, U.S. Pat. No. 8,026,521B1 and U.S. Patent Publication No. 2010/0276662A1 disclose field effect transistors having a junctionless structure without forming the source/drain regions.
However, the junctionless field effect transistors developed so far, as shown in FIG. 2, are consisted of a buried oxide (BOX) 100 disposed on the base for blocking the leakage current, an active region of a thin silicon layer 200 doped with doping concentration higher than 1×1019/cm3 for a device operation and a structure of source and drain electrodes 500 and 600 contacted directly on the silicon layer 200 in both ends of a gate electrode 400 without additional formation of the source/drain regions.
Therefore, the junctionless field effect transistors developed so far have big problems on the two points as follows:
First, fabrication costs for the prior junctionless field effect transistors are expensive. Since the prior junctionless field effect transistors need a BOX 100 and a thin silicon layer 200 on the BOX 100 for getting the full control ability of a gate, it must use an SOI (silicon-on-insulator) substrate 10 times or higher than the cost of a bulk silicon substrate.
Second, the low power operation of the prior junctionless field effect transistors is difficult. Since the prior junctionless field effect transistors need an SOI substrate having a silicon layer 200 doped with doping concentration higher than 1×1019/cm3, the high doping level reduces electron mobility remarkably and has difficulty in providing an driving current with a needed level. For a specific high level of the driving current, it must be needed to apply a high driving voltage.